1. The interrupt for which the processor has highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
a) high
b) low
c) high or low
d) unchanged
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
a) set
b) reset
c) high
d) low
a) low
b) high
c) low or high
d) none of the mentioned
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the external interrupts.
2. The interrupt for which the processor has highest priority among all the internal interrupts isExplanation: The Non-Maskable Interrupt input pin has the highest priority among all the external interrupts.
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts except the Divide By Zero (Type 0) exception.
3. In case of string instructions, the NMI interrupt will be served only afterExplanation: TRAP is the internal interrupt that has highest priority among all the interrupts except the Divide By Zero (Type 0) exception.
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and then NMI is served. In case of string instructions, it is served after the complete string is manipulated.
4. The NMI pin should remain high for atleastExplanation: When NMI is activated, the current instruction being executed is completed and then NMI is served. In case of string instructions, it is served after the complete string is manipulated.
a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be synchronized with the clock for being sensed.
5. The INTR signal can be masked by resetting theExplanation: The NMI pin should remain high for atleast 2 clock cycles and need not be synchronized with the clock for being sensed.
a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.
6. For the INTR signal, to be responded to in the next instruction
cycle, it must go …….. in the last clock cycle of the current
instructionExplanation: The INTR signal can be masked by resetting the interrupt flag.
a) high
b) low
c) high or low
d) unchanged
Answer: a
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order to respond in the next instruction cycle.
7. The status of the pending interrupts is checked atExplanation: The INTR signal must go high in the clock cycle of the current instruction in order to respond in the next instruction cycle.
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.
8. Once the processor responds to an INTR signal, the IF is automaticallyExplanation: At the end of each instruction, the status of the pending interrupts is checked.
a) set
b) reset
c) high
d) low
Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the processor wants to respond to any type of INTR signal further then, the IF should again be set.
9. If the pin LOCK (active low based) is low at the trailing edge of
the first ALE pulse, then till the start of the next machine cycle, the
pin LOCK (active low) isExplanation: The IF is automatically reset when the processor responds to an INTR signal. If the processor wants to respond to any type of INTR signal further then, the IF should again be set.
a) low
b) high
c) low or high
d) none of the mentioned
Answer: a
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.
10. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in it forExplanation: The pin LOCK (active low) remains low till the start of the next machine cycle.
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
Answer: c
Explanation: The INTA (active low) goes low and remains low for two clock cycles before returning back to the high state.
Explanation: The INTA (active low) goes low and remains low for two clock cycles before returning back to the high state.
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